Computer graphics display systems, e.g., CAD/CAM graphics workstations, are widely used to generate and display two-dimensional images of three-dimensional objects for scientific, engineering, manufacturing and other applications. In such high performance computer graphics systems, digital representations of computer generated images conventionally reside in an array of video RAM, which collectively embody the system frame buffer. The rate at which the frame buffer can be updated is a critical parameter in the performance of the entire graphics system. With the ever increasing use of engineering/scientific graphics workstations, there is a need to perform ever more complex rendering algorithms.
Displaying three-dimensional objects on a two-dimensional display device in part requires a graphics system to recognize and eliminate hidden surfaces and lines to obtain the desired three-dimensional effect. One popular method for eliminating hidden surfaces of an image to be rendered involves the use of a depth buffer or Z-buffer. A Z-buffer is a large array of memory with an entry for each picture element, or pixel, on the graphics system's display device.
The Z-axis in a graphics system reflects the distance from a specified observer's viewpoint. Thus, for example, a larger Z value may be defined to represent a greater distance from a viewpoint. A comparison of Z values of points on generated objects determines which object is closest to the viewpoint and therefore which object should appear on the two dimensional display. In Z-buffer systems, as each pixel is generated its Z coordinate (ZNEW) is compared with the Z coordinate previously stored in the Z-buffer (ZOLD). If ZOLD does not exist, then ZNEW is compared to the Z coordinate of the background. If ZNEW is less than ZOLD (indicating in the present example that the pixel is closer to the viewpoint than the previous pixel), then the pixel is written to the display device and the Z-buffer memory is updated to contain ZNEW. If ZNEW is greater than or equal to ZOLD, then the pixel is not written and the Z-buffer remains unchanged. A description of the Z-buffer technique is presented by J. D. Foley and A. Van Dam, in Fundamentals of Interactive Computer Graphics, Addison-Wesley Publishing Co., pp. 560-561 (1982).
The use of a Z-buffer simplifies the solution of the hidden surface problem, however, the speed at which the Z-buffer memory can read, compare and update limits the graphics system pixel writing speed. The large amount of memory required, typically one megabyte or more, and the cost of these devices normally dictates the use of dynamic random access memory (DRAM) instead of more costly static random access memory (SRAM). Commercially available DRAMs may, for example, have read-modify-write (RMW) cycle times on the order of 200 nanoseconds (ns). However, the typical computer graphics processor is capable of generating pixel data at higher speeds, e.g. 100 nanoseconds per pixel, and a display device is capable of receiving pixel data at equally high speeds. Therefore, the slow RMW cycle of the DRAM for Z-buffering is a limiting factor on the ability to speed the display generation process. Thus, in conventional frame buffer designs, read-modify-write operations decrease frame buffer bandwidth and overall system performance.
Various approaches to enhancing frame buffer bandwidth have been proposed. For example, in U.S. Pat. No. 4,679,041, entitled "High Speed Z-Buffer With Dynamic Random Access Memory", issued to Fetter et al., a system which overlaps the ZNEW calculation with the ZOLD read-modify-write cycle is described. In another patent, U.S. Pat. No. 5,043,921, entitled "High Speed Z-Buffer Control", issued to Gonzalez-Lopez et al. and assigned to the same assignee as the present invention, a rapid comparison of values by comparing blocks of Z values with each cycle is discussed. The most straightforward approach to improving performance is to divide the entire frame buffer into two separate devices so that the characteristics of adjacent pixels can be alternately stored in different ones of the two devices. In this way, read-modify-write operations on different but adjacent pixels can be overlapped thereby increasing processing performance. The difficulty with this approach, however, is that twice the number of pins are required of the raster engine to access the dual devices. This requirement proves in practice to be a significant complication.
Packaging technology has been improving almost linearly over the last decade, while memory/logic technology has expanded exponentially. Thus, the density of available pin packaging is an ever more important consideration in the implementation of a high performance computer system, such as a graphics display system.
Therefore, a need exists in the graphics display industry for enhanced frame buffer throughput (and in particular, for enhanced performance of read-modify-write cycles used in the implementation of the conventional Z-buffering technique) while, to the extent possible, minimizing the number of I/O pins utilized by the raster engine to attain the enhanced processing.